b'/* Copyright (c) 2014, Fortylines LLC\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR\n CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n/*\n This file implements a 4-bit ripple carry adder bundled with an exhaustive\n testbench.\n\n Simulate with iverilog:\n\n $ iverilog 4-bit-ripple-carry-adder.v\n $ ./a.out\n\n*/\n\nmodule half_adder(\n output sum, carry_out,\n input left, right\n);\n assign sum = left ^ right;\n assign carry_out = left & right;\n\nendmodule // half_adder\n\n\nmodule full_adder(\n output sum, carry_out,\n input left, right, carry_in\n);\n wire sum1, carry1, carry2;\n half_adder ha1(sum1, carry1, left, right);\n half_adder ha2(sum, carry2, sum1, carry_in);\n assign carry_out = carry1 | carry2;\n\nendmodule // full_adder\n\n\nmodule ripple_adder_4bit(\n output [3:0] sum,\n output carry_out,\n input [3:0] left, right,\n input carry_in\n);\n wire carry1, carry2, carry3;\n full_adder fa1(sum[0], carry1, left[0], right[0], carry_in);\n full_adder fa2(sum[1], carry2, left[1], right[1], carry1);\n full_adder fa3(sum[2], carry3, left[2], right[2], carry2);\n full_adder fa4(sum[3], carry_out, left[3], right[3], carry3);\n\nendmodule // ripple_adder_4bit\n\n\nmodule test_adder_4bit;\n // inputs\n reg [3:0] left;\n reg [3:0] right;\n reg carry_in;\n // outputs\n wire [3:0] sum;\n wire cary_out;\n\n ripple_adder_4bit adder(\n .sum(sum),\n .carry_out(carry_out),\n .left(left),\n .right(right),\n .carry_in(carry_in)\n );\n\n initial begin\n left = 0;\n right = 0;\n carry_in = 0;\n\n #50; // wait for reset to complete\n\n // exhaustive testing, going through all combinations.\n while (left < 15) begin\n while (right < 15) begin\n #10 right = right + 1;\n end\n #10 left = left + 1; right = right + 1;\n end\n while (right < 15) begin\n #10 right = right + 1;\n end\n #10 left = left + 1; right = right + 1; carry_in = 1;\n while (left < 15) begin\n while (right < 15) begin\n #10 right = right + 1;\n end\n #10 left = left + 1; right = right + 1;\n end\n while (right < 15) begin\n #10 right = right + 1;\n end\n\n end // initial begin\n\n initial begin\n $monitor("time=", $time,,\n "left=%b right=%b carry_in=%b : sum=%b carry_out=%b",\n left, right, carry_in, sum, carry_out);\n /* The following statement will (by default) create a dump.vcd\n when the testbench is executed by iverilog. */\n $dumpvars(0, test_adder_4bit);\n end\n\nendmodule // test_adder_4bit\n\n'